Lattice Semiconductor Enables Rapid Prototyping of Smart Connectivity Designs with ECP5 Versa Development Kit
Promotional Offer Now Available for New ECP5™
-
ECP5 Versa development kit and Lattice Diamond software promotional
offer now available for
$99 for a limited time - ECP5 family offers low power consumption, small form factor and low cost FPGAs for flexible connectivity to ASICs and ASSPs
- ECP5 devices are targeted for small cells, microservers, broadband access, and industrial video
To help customers interested in the ECP5 device family to quickly design and test application prototypes, Lattice has released an ECP5 Versa development kit. The kit lets customers evaluate the connectivity performance of the ECP5 FPGA with a range of standards, including PCI Express, Gigabit Ethernet, DDR3 and generic SERDES. Lattice also offers several proof-of-concept demos with the ECP5 Versa development kit that can help customers accelerate prototyping and testing of their designs.
Additionally, the ECP5 Versa development kit includes the Lattice Diamond Design Software that offers a complete suite of FPGA design tools with an easy-to-use interface, efficient design flow, superior design exploration and more. The Lattice Diamond software suite tailored specifically for the ECP5 Versa kit will be available free of charge to all users purchasing the board.
The new ECP5 Versa development kit is available direct from Lattice at a
limited promotional price of
“When we developed the ECP5 family, we broke all the rules of
conventional FPGA approaches in order to deliver the optimum
connectivity solution tailored to meet the demands of compact, low
power, high volume communications and industrial applications,” said
Lattice optimized the ECP5 family’s architecture with the goal of delivering the best value below 100K LUTs, while adding key new features such as support for soft error correction, and small form factor packages across all densities. Achieving 40% lower cost than competing solutions, optimizations include small LUT4 based logic slices with enhanced routing architecture, dual-channel SERDES to save silicon real estate, and enhanced DSP blocks for up to 4x resource improvements.
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