Lattice FPGAs with High I/O Density Bring Low Power Signal Bridging and Interface Management to Edge Devices
New Lattice MachXO2ZE FPGA Options Deliver High Density I/O Support at Small Size,
According to Glenn O’Donnell, Vice President and Research Director at Forrester Research, “In 2020, the COVID-19 pandemic produced few net-new technology and business developments, but it certainly accelerated many technology trends already in motion. Edge computing is one of the most notable among these accelerated technologies.”1
“Most Edge computing applications require sensor data to enable their users’ connected experiences, be it a microphone in a smart speaker capturing a voice command or a hand-held RFID scanner scanning a barcode in a warehouse,” said
These new Lattice MachXO2ZE variants combine a low-power, small form factor FPGA fabric with Embedded Block RAM (EBR), Distributed RAM, and User Flash Memory (UFM) blocks developers can use to implement a variety of functions in high-volume Edge devices. Other capabilities such as robust I/O support (1.2 to 3.3V), low-voltage differential signaling (LVDS), and integrated phase lock loops (PLLs) further broaden the scope of applications these devices can support.
Two new MachXO2ZE devices are available in the WLCSP packaging, offering 1,200 and 4,000 LUTs in either a 2.5 x 2.5 mm (28 GPIO) or a 3.8 x 3.8 mm (63 GPIO) sized package.
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Lattice is a long-standing leader in low power programmable logic for signal bridging, interface management, and secure system control. Mach FPGAs have an attach rate of over 80 percent on current shipping server platforms, and are used in a range of communications/compute, industrial, automotive, and consumer applications.
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1 https://go.forrester.com/blogs/predictions-2021-edge-computing-hits-an-inflection-point/
View source version on businesswire.com: https://www.businesswire.com/news/home/20210210005857/en/
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